Interconnection Structure (Computer Architecture)

The interconnection structure must support the following types of module

• Memory to processor : the CPU reads an instruction or data from memory
• Processor to memory : the CPU write data to memory 
• I/O to processor : the CPU reads data from the I/O device via the I/O module 
• Processor to I/O
• I/O to or from memory : An I/O module is allowed to change data directly with memory without going through the processor using DMA (Direct Memory Access) 

Bus Interconnection 

• A bus is a  communication pathway consisting of lines and it is connecting two or more devices. 
• A bus is considered as a shared transmission medium allowing multiple devices to connect to it
• However, only one device at a time can successfully transmit 
• Several lines of the bus can be used to transmit binary digits simultaneously. 
• For example : 
• An 8 bit unit of data can be transmitted over 8-bus lines. 
• A bus that connect the major computer components (CPU, Memory, I/O) is called System Bus. 
• A system bus may consists of 50 or hundreds of separate lines. Each line has a particular functions. 

• The interconnection structures are based on the use of one or more system buses. 
• Bus lines can be classified based 3 functional groups. 

Bus lines can be classified based on 3 functional groups. 

1. Data Lines
2. Address Lines 
3. Control Lines

Data Lines

• It provide pathway for moving data between system modules. 
• These lines are called Data Bus
• The Lines (32 to hundred) referred to as the width of the bus
• The width determines the overall system performance. 

e.g If the data bus is 8 bit wide, and each instruction is 16 bit long, then the processor must access the memory module twice during each instruction cycle. 

Address Line

• It is used to determine the source or destination of the data on the data bus. 
• For example : 
• The CPU puts the address of the desired word to be read from/or written to memory on the address lines. 
• The width of an system bus determine the maximum addressable memory
• The address lines are also used to address I/O ports. 

Control Lines

• Control lines are used to hold control signals to control the access and the use of data and address lines since these lines are shared by all components
• Control signals transmit command and timing information between system components. 
• Timing signal indicate the validity of data and address information 
• Command signals specifies the type of operations to be performed

Main operation of Bus 
If a module wishes to send data to another module it must do two things.

• Obtain the use of the bus
• Transfer data via the bus

If a module wishes to request data from another module it must do two things. 

• Obtain the use of the bus
• Transfer a request to the other module over appropriate control and address lines
• Wait for the other module to send the data