Memory Hierarchy and Cache Memory Mapping Functions

Memory Hierarchy, Cache Memory Mapping Functions, Memory Hierarchy and Cache Memory Mapping Functions, Define memory hierarchy. Explain cache memory mapping functions with example, MICT CA Notes, MICT 1st sem CA Notes, MICT Computer notes, MICT CA Notes, Computer Architecture notes,

Define memory hierarchy. Explain cache memory mapping functions with example.

Memory hierarchy is a concept that is necessary for the CPU to be able to manipulate data. In computer architecture, the memory hierarchy separates computer storage into a hierarchy based on response time. Since response time, complexity, and capacity are related, the levels may also be distinguished by their performance and controlling technologies. The following figure shows the hierarchy of memory in computer.

Cache is used by the CPU for memory which is being accessed over and over again. Instead of pulling it every time from the main memory, it is put in cache for fast access. It is also a smaller memory, however, larger than internal register.

Cache memory is used to reduce the average time to access data from the Main memory. The cache is a smaller and faster memory which stores copies of the data from frequently used main memory locations.

There are different levels of catch memory. Level 1, Level 2, Level 3 etc. Levels of catch is based on the architecture of computer.

Cache Mapping
There are three different types of mapping used for the purpose of cache memory which are as follows:

Direct mapping
Associative mapping and
Set-Associative mapping.

Direct Mapping

Direct catch mapping

The simplest way to determine cache locations in which store Memory blocks is direct Mapping technique.
In this block J of the main memory maps on to block J modulo 128 of the cache. Thus main memory blocks 0,128,256,….is loaded into cache is stored at block 0. Block 1,129,257,….are stored at block 1 and so on.
Placement of a block in the cache is determined from memory address. Memory address is divided into 3 fields, the lower 4-bits selects one of the 16 words in a block.

When new block enters the cache, the 7-bit cache block field determines the cache positions in which this block must be stored.
The higher order 5-bits of the memory address of the block are stored in 5 tag bits associated with its location in cache. They identify which of the 32 blocks that are mapped into this cache position are currently resident in the cache.
It is easy to implement, but not Flexible