RISC Pipeline (Computer Architecture)
Reduced instruction set computer (RISC).
The main characteristics of RISC pipeline is to use an efficient instructions pipeline. In case of RISC pipeline, the instruction pipeline can be implemented with only two or three segments where segments 1 fetches the instructions from the memory.
Segment 2 executes the instruction in the ALU, and segment 3 may be used to store the results of the ALU operation in a particular register.