Types of Instruction Format (CA Assignment)
The number of address fields in the instruction format depends on the internal organization of CPU. On the basis of no. of address field, we can categories the instruction as bellow.- Three Address Instruction : Memory addresses for the two operands and one destination need to be specified. It is also called General register organization.
- Two Address Instruction : Two address registers or two memory locations are specified. Assumes that the destination address is the same as that of the first operand.
- One Address Instruction : One address can be a register name or memory address. It uses AC (Accumulator) register for all data manipulation. It is also called single accumulator organization.
- Zero Address Instruction : Stack is used. Arithmetic operation pops two operands from the stack and pushes the result. It is also called stack organization.
CA Assignment (MICT 1st Sem)
Write instruction of following expression using 3, 2, 1 and 0 address instruction format.
a) Y = (A+B) * C
Three (3) address instruction format
ADD R1, A, B // R1 = M[A] + M[B]
MUL Y, R1, C // M[Y] = R1 * M[C]
Two (2) address instruction format
MOV R1, A // R1 = A
ADD R1, B // R1 = R1 + M[B]
MOV R2, C // R2 = M[C]
MUL R1, R2 // R1 = R1 * R2
MOV Y, R1 // M[Y] = R1
One (1) address instruction format
LOAD A // AC = M[A]
ADD B // AC = AC + M[B]
MUL C // AC = AC * M[C]
STORE Y // M[Y] = AC
Zero (0) address instruction format
PUSH A // TOS = M[A]
PUSH B // TOS = M[B]
ADD // TOS = M[A] + M[B]
PUSH C // TOS = M[C]
MUL // TOS = (M[A] + M[B]) * M[C]
POP Y // M[Y] = TOS
b) Z = (A*C+D)*A
Three (3) address instruction format
MUL R1, A, C // R1 = M[A] * M[C]
ADD R2, R1, D // R2 = R1 + M[D]
MUL Z, R2, A // M[Z] = R2 * M[A]
Two (2) address instruction format
MOV R1, A // R1 = M[A]
MUL R1, C // R1 = R1 * M[C]
MOV R2, D // R2 = M[D]
ADD R1, R2 // R1 = R1 + R2
MUL R1, A // R1 = R1 * M[A]
MOV R1, Z // M[Z] = R1
One (1) address instruction format Z = (A*C+D)*A
LOAD A // AC = M[A]
MUL C // AC = AC * M[C]
ADD D // AC = AC + M[D]
MUL A // AC = AC * M[A]
STORE Z // M[Z] = AC
Zero (0) address instruction format
PUSH A // TOS = M[A]
PUSH C // TOS = M[C]
MUL // TOS = M[A] * M[C]
PUSH D // TOS = M[D]
ADD // TOS = (M[A] * M[C]) + M[D])
PUSH A // TOS = M[A]
MUL // TOS = (M[A] * M[C]) + M[D]) * M[A]
POP Z // M[Z] = TOS
c) Y = {(A+B)*C}+D
Three (3) address instruction format
ADD R1, A, B // R1 = M[A] + M[B]
MUL R2, R1, C // R2 = R1 * M[C]
ADD Y, R2, D // M[Y] = R2 + M[D]
Two (2) address instruction format
MOV R1, A // R1 = M[A]
ADD R1, B // R1 = R1 + M[B]
MOV R2, C // R2 = M[C]
MUL R1, R2 // R1 = R1 * R2
MOV R3, D // R3 = M[D]
ADD R1, R3 // R1 = R1 + R3
MOV Y, R1 // M[Y] = R1
One (1) address instruction format (Y = {(A+B)*C}+D)
LOAD A // AC = M[A]
ADD B // AC = AC + M[B]
STORE T // M[T] = AC
LOAD C // AC = M[C]
MUL T // AC = AC * M[T]
ADD D // AC = AC + M[D]
STORE Y // M[Y] = AC
Zero (0) address instruction format
PUSH A // TOS = M[A]
PUSH B // TOS = M[B]
ADD // TOS = M[A] + M[B]
PUSH C // TOS = M[C]
MUL // TOS = (M[A]+M[B])*M[C]
PUSH D // TOS = M[D]
ADD // TOS = {(M[A]+M[B])*M[C]}+M[D]
POP Y // M[Y] = TOS
