Info-Grade

Cache Coherence

In a shared memory multiprocessor with a separate cache memory for each processor, it is possible to have many copies of any one instruction operand. One copy in the main memory and one in each cache memory. When one copy often operand is changed, the other copies of the operand must be changed.

For example :

In the above illustration, consider both the processor have a cache copy of a particular memory block from previous read. Let suppose processor 1 updates or change the cache block, after that it change the memory block using any one methods (write through, write block or instruction flow). But processor doesn't get any notification or signals of update/change. So here data inconsistency occurs, it is called cache coherence. It happens in multiprocessor system.

Cache coherence occurs in the following conditions

* Inconsistency in sharing of writable data

* Inconsistency in process migration

* IO Activity

There are three distinct levels of cache coherence:

Every write operation appears to occur instantaneously.
All processes see exactly the same sequence of changes of values for each separate operand.
Different processes may see an operand assume different sequences of values. (This is considered non-coherent behavior.)

Types of cache coherence solution

To avoid cache coherence we have two types of solution

Software Solution
Hardware Solution

Software Solution

- Problem is managed completely by compiler and OS.

- No additional circuitry

- In this approach, compiler marks the data which are likely to be changed, the OS prevent those data to be cached.

Hardware Solution

- Hardware solution provide dynamic recognition at run time of potential inconsistency conditions. Because the problem is only dealt with when it actually arises, there is more effective use of caches, leading to improved performance over a software approaches.

- Hardware schemes can be divided into two categories

Directory Protocol
Snoopy protocols

Snooping

- Used with low-end MPs

- Few processors

- Centralized memory

- Bus-based

- Distributed implication : responsibility for maintaining coherence lies with each cache

Direct

- Used with higher-end MPs

- More processors

- Distributed memory

- Multi-path interconnect

- Centralizing for each address : responsibility for maintaining coherence lies with the directory for each address

Pipelining Hazards

Define arithmetic pipelining. Explain pipelining hazards with examples.

Pipelining is a technique where multiple instructions are overlapped during execution. Pipeline is divided into stages and these stages are connected with one another to form a pipe like structure. Instructions enter from one end and exit from another end. There are two types of pipeline.

Arithmetic Pipeline
Instruction Pipeline

Arithmetic pipelines are usually found in most of the computers. They are used for floating point operations, multiplication of fixed point numbers etc.

Pipeline hazards are situations that prevent the next instruction in the instruction stream from

Pipelining Hazards

Pipeline hazards are situations that prevent the next instruction in the instruction stream from executing during its designated clock cycles. In another word, any condition that causes a stall in the pipeline operations can be called a hazard. There are mainly three types of hazards, They are :

Data Hazards
Control Hazards or instruction Hazards
Structural Hazards.

Example:

A=3+A

B=A*4

For the above sequence, the second instruction needs the value of ‘A’ computed in the first instruction. Thus the second instruction is said to depend on the first. In this situation data hazards is arises. A data hazard is any condition in which either the source or the destination operands of an instruction are not available at the time expected in the pipeline.

Memory Hierarchy and Cache Memory Mapping Functions

Define memory hierarchy. Explain cache memory mapping functions with example.

Memory hierarchy is a concept that is necessary for the CPU to be able to manipulate data. In computer architecture, the memory hierarchy separates computer storage into a hierarchy based on response time. Since response time, complexity, and capacity are related, the levels may also be distinguished by their performance and controlling technologies. The following figure shows the hierarchy of memory in computer.

Cache is used by the CPU for memory which is being accessed over and over again. Instead of pulling it every time from the main memory, it is put in cache for fast access. It is also a smaller memory, however, larger than internal register.

Cache memory is used to reduce the average time to access data from the Main memory. The cache is a smaller and faster memory which stores copies of the data from frequently used main memory locations.

There are different levels of catch memory. Level 1, Level 2, Level 3 etc. Levels of catch is based on the architecture of computer.

Cache Mapping
There are three different types of mapping used for the purpose of cache memory which are as follows:

Direct mapping
Associative mapping and
Set-Associative mapping.

Direct Mapping

Direct catch mapping

The simplest way to determine cache locations in which store Memory blocks is direct Mapping technique.
In this block J of the main memory maps on to block J modulo 128 of the cache. Thus main memory blocks 0,128,256,….is loaded into cache is stored at block 0. Block 1,129,257,….are stored at block 1 and so on.
Placement of a block in the cache is determined from memory address. Memory address is divided into 3 fields, the lower 4-bits selects one of the 16 words in a block.

When new block enters the cache, the 7-bit cache block field determines the cache positions in which this block must be stored.
The higher order 5-bits of the memory address of the block are stored in 5 tag bits associated with its location in cache. They identify which of the 32 blocks that are mapped into this cache position are currently resident in the cache.
It is easy to implement, but not Flexible

Divide 21 by 6 using restoring Two's complement method

Organization of Micro-Programmed Control design

Explain the Organization of micro-programmed control design.

Micr-program is a process of writing microcode for a microprocessor. Microcode is low-level code that defines how a microprocessor should function when it executes machine-language instructions. Typically, one machine language instruction translates into several microcode instruction, on some computers, the microcode is stored in ROM and can not be modified.

Micro programmed Control Unit:

A control unit with its binary control values stored as words in memory is called as micro programmed control. Each word in the control memory contains micro instruction that specifies one or more micro operations for the system. A sequence of micro instructions constitutes a micro program.
Micro programmed implementation is a software approach in contrast to the hardwired approach.
It deals with various units of software but at the micro level i.e. micro-operation, micro-instruction, micro-program etc.
Different key elements used for implementation of a control unit using micro programmed approach is shown in fig. below:

Control Address Register (CAR)

It contains the address of next micro instruction to be read. This is similar to the program counter(PC) which stores the address of the next instruction.

Control Memory

The set of micro instruction is stored in control Memory (CM) also called as control store.

Control Buffer Register(CBR)

When microinstruction is read from the control memory, it is transferred to a control Buffer Register (CBR), which is similar to the instruction Register (IR) that stores the opcode of the instruction read from the memory.

Sequencing

It loads the control Address register with the address of the next instruction to be read abd issues a read command to control memory.

Instruction Execution Cycle

Explain the instruction execution cycle with state diagram.

The instruction cycle is the cycle which the central processing unit (CPU) follows from boot-up until the computer has shut down in order to process instructions. It is also known as the fetch–decode–execute cycle or simply the fetch-execute cycle. It is composed of three main stages: the fetch stage, the decode stage, and the execute stage. In an improved instruction execution cycle, we can introduce a next cycle known as the interrupt cycle.

Fetch

It is the process of obtaining instructions from the memory. The next instruction is fetched from the memory address that is currently stored in the PC (program counter) and stored into the IR (instruction register). At the end of the fetch operation, the PC points to the next instruction that will be read at the next cycle.

Decode

It is the stage of understanding the instructions. During this stage the encoded instruction present in the instruction register is interpreted by the decoder.

Execute

In this stage control unit sends the instructions and data to ALU for taking suitable action on the instruction and writing the result back to a register. If the ALU is involved, it sends a condition signal back to the CU. The result generated by the operation is stored in the main memory or sent to an output device.

Repeats Cycle

Once the execution cycle is complete, It repeats the same process/cycle for the next instruction.