Info-Grade

Traditional memory stores data at a specific address and "recalls" that data later if the address is specified. Instead of an address, associative memory can recall data if a small portion of the data itself is specified.


Associative memory is often referred to as content. Addressable memory (CAM). In associative memory, any stored items can be accessed by using the contends of item. Items are stored in an associative memory have two field format, key and data.
Associative searching is based on simultaneous matching of key to be searched with stored key associated with each line of data.



The following diagram shows the block representation of an associative memory.

The functional registers like the argument register A and key register K each have n bits, are for each bit of a word. The match register m consist of M bits, one for each memory word.

Pipeline hazards are situations that prevent the next instruction in the instruction stream from executing during its designated clock cycles. In another word, any condition that causes a stall in the pipeline operations can be called a hazard. There are mainly three types of hazards, they are:

1. Data Hazards 
2. Structural Hazards
3. Control Hazards 

Data Hazards
It arises when instructions depend on the result of previous instruction but the previous instruction is not available yet.

Structural Hazards:
They arise when there are resource conflicts that prevents hardware to execute simultaneous execution of instruction. For e.g. Lets say the hardware has a register file which has a limitation of only one read or write in a cycle. If there is an instruction that needs to read from this register file while another instruction needs to write to this register file, only one can execute because of conflict.

Control Hazards
These hazards arise as a result of any type of branch instruction. Till the branch is completely executed. The branch is completely executed, the stream of following instructions will not be known completely.

Reduced instruction set computer (RISC).
 The main characteristics of RISC pipeline is to use an efficient instructions pipeline. In case of RISC pipeline, the instruction pipeline can be implemented with only two or three segments where segments 1 fetches the instructions from the memory.

Segment 2 executes the instruction in the ALU, and segment 3 may be used to store the results of the ALU operation in a particular register.

Parallel processing systems are designed to speed up the execution of programs by dividing the program into multiple fragments and processing these fragments simultaneously such systems are known as tightly coupled systems.


Parallel computing is an evolution of serial computing where the jobs are broken into discrete parts that can be executed currently. Each part is further broken down to a series of instructions. Instructions from each part execute simultaneously on different CPU's.


Parallel systems are more difficult to program than computers with a single processor because the architecture of parallel computers varies accordingly and the processes of multiple CPU's must be co-ordinates and synchronized.

Pipeline is the process of accumulating instruction from the process through a pipeline. It allows strong and executing instructions in an orderly process. It is also known as pipeling process.

Pipeline is a technique where multiple instructions are overlapped during execution. Pipeline is divided into stages and these stages are connected with one another to form a pipe like structure. Instructions entered from one end and exit from another end.

1. Arithmetic Pipeline 
2. Instruction Pipeline 

Here, A and B are significant digits of floating point number, while a and b are exponents.


Instruction Pipeline
In this a stream of instructions can be executed by overlapping fetch, decode and execute phases of an instruction cycle. This type of technique is used to increases the throughput of the computer system.

An instruction pipeline reads instruction from the memory while previous instructions are being executed in other segments of the pipeline. Thus we can execute multiple instructions simultaneously. The pipeline will be more efficient if the instruction cycle is divided into segment of equal duration.

The interconnection structure must support the following types of module

• Memory to processor : the CPU reads an instruction or data from memory
• Processor to memory : the CPU write data to memory 
• I/O to processor : the CPU reads data from the I/O device via the I/O module 
• Processor to I/O
• I/O to or from memory : An I/O module is allowed to change data directly with memory without going through the processor using DMA (Direct Memory Access) 

Address Line

• It is used to determine the source or destination of the data on the data bus. 
• For example : 
• The CPU puts the address of the desired word to be read from/or written to memory on the address lines. 
• The width of an system bus determine the maximum addressable memory
• The address lines are also used to address I/O ports. 

Control Lines

• Control lines are used to hold control signals to control the access and the use of data and address lines since these lines are shared by all components
• Control signals transmit command and timing information between system components. 
• Timing signal indicate the validity of data and address information 
• Command signals specifies the type of operations to be performed

Main operation of Bus 
If a module wishes to send data to another module it must do two things.

• Obtain the use of the bus
• Transfer data via the bus