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May 21, 2019 , ,

RISC (Reduced Instruction Set Computer) Processor

RISC is known as Reduced instruction Set Computer. It is a type of microprocessor that has limited number of instructions. It can execute it's instructions very fast because instructions are very small and simple. 

RISC chips require fewer transistors which make them cheaper to design and produce. Most Instructions complete in one cycle, which allows the processor to handle many instructions at same time. In this type of processor, instructions are register based and data transfer takes place from register to register. 
Features of RISC
  • Simple and small instruction
  • Instruction come under size of one word
  • Instruction take single clock cycle to get executed
  • Simple addressing modes
  • Less data types
  • Pipeline can be achieved
  • More number of general purpose register


CISC (Complex Instruction Set Computer) Processor 

CISC is known as Complex Instruction Set Computer. It was first developed by Intel corporation. It contains large number of complex instructions. In this processor instructions are not register based and instructions cannot be completed in one machine cycle. Data transform is from memory to memory. Micro programmed control unit is found in CISC. It also have variable instruction format. 
Features of CISC
  • Complex instruction, hence complex instruction decoding
  • Instruction may take more than single clock cycle to get executed
  • Instruction are larger than one word size
  • Complex addressing mode
  • More data types 
Difference Between CISC and RISC 


RISC CISC
  • It has Large set of instructions with variable formats
  • Data transfer is from register to register.
  •  Instruction are register based.
  •  It takes less memory access
  • It includes single clock. 
  • Instructions are reduced and simple. 
  • It has small set of instructions with fixed format
  • Data transfer is from memory to memory
  • Instructions are not memory based. 
  • It takes more memory access
  • It includes multi clocks. 
  • Instructions are complex. 
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May 15, 2019 , , ,
It specifies a rule for interpreting or modifying the address field of the instruction before the operand is actually referenced. It helps for 
  • Providing programming flexibility to the uses.
  • Using the bits in the address field of instruction efficiently

Types of Addressing Modes

1) Implied Addressing Mode
  • Address of operands are specified implicit in the definition of instruction.
  • It does not need to specify address of instruction
  • Example : Add x; Add y; 
2) Immediate Addressing Mode: 
  • Instead of specifying the address of operand itself is specified in the instruction. 
  • No need to specify address in the instruction. 
  • However, operand itself need to be specified. 
  • Sometimes, require more bits to be address. 
  • Fast to acquire an operand
3) Register Addressing Mode
  • Address specified in the instruction is the address of register.
  • The instruction has the address of the Register where the operand is stored.
  • Shorter address then memory address.
  • Shorter instructions and faster instruction fetch
  • Saving address field to access to the operands 
  • It has very limited address space
4) Register Indicate Addressing Mode
  • In this mode, the instruction specifies the register whose contents give us the address of operand which is in memory. Thus the register contains the address of operand rather than the operand itself. 
  • Instruction specifies a register which contains the memory address of operand 
  • Saving instruction bits since register address is shorter than memory address
  • Slower then register and memory addressing 
  • Example:   EA = contend of R
5) Auto increment or Auto Decrement address mode
  • In this mode the register is increment or decremented after or before its value is used. 
  • Instruction specifies the memory address which can be used directly to access the memory. 
  • Faster then the memory addressing mode
  • Too many bits are needed to specify the address for a physical memory space.
  • Example:   EA = IR (Address)
6) Direct Addressing Mode
  • In this mode, effective address of operand is present in instruction itself. 
  • Single memory reference to access data
  • No additional calculation to find the effective address of the operand
  • For Example: Add R1, 4000, In this the 4000 is effective address of operand.  
        Note : Effective Address is the location where operand is present
7) Indirect Addressing Mode
  • The address field of an instruction specifies the address of a memory location that contains the address of the operand. 
  • When the abbreviated address is used large physical memory can be addressed with the relatively small number of bits.
  • Slow acquire operand because of an additional memory access. 
  • Example:    EA = M[IR )address)]
8)  Relative Addressing Mode
The address field of instruction specifies the part of the address which can be used along with a designed register to calculate the address of the operand. 
  • Address field of the instruction is short
  • Large physical memory can be accessed with a small number of address bits.
  • There are three addressing mode
There are three different other register addressing mode:
  1. PC Relative addressing Mode (EA = IX + IR(address))
  2. Indexed Addressing Mode (EA = IX + IR (address)) / [IX is indexed register]
  3. Base Register Addressing Mode (EA = A + (R) 
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May 11, 2019 , , ,

A number system is a system for expressing numbers that is mathematical notation used for manipulating other countable things. The numbers are represented in different based system in different situation. The decimal number system is used for human counting but not role in machines. Binary numbers are used in modern digital devices. Octal and Hexadecimal number system are just packages of 4 binary bits. In computer science we have to study four number systems. They are


  1. Binary Number System (0, 1) / Base or radix = 2
  2. Octal Number System (0 to 7) Base or radix = 8
  3. Decimal Number System (0 to 9) Base or radix = 10
  4. Hexadecimal Number System (0 to 9 and A to F) Base or radix = 16
The following table shows the number system equivalent to one another. 
Binary
Octal
Decimal
Hexadecimal
0000
0
0
0
0001
1
1
1
0010
2
2
2
0011
3
3
3
0100
4
4
4
0101
5
5
5
0110
6
6
6
0111
7
7
7
1000
10
8
8
1001
11
9
9
1010
12
10
A
1011
13
11
B
1100
14
12
C
1101
15
13
D
1110
16
14
E
1111
17
15
F


  1. Binary Number System : Any number having base or radix 2 and the number consists 0 and 1 only are called binary number system. E.g:  1110­2, 10012, 1110012
  2. Decimal Number System: Any number having base or radix 8 and the number consists 0, 1, 2, 3, 4, 5, 6 and 7 are called octal number system. E.g: 563­8, 12358, 57368
  3. Decimal Number System: Any number having base or radix 10 and the numbers consists 0, 1, 2, ........ 9 are called decimal number system. E.g : 196­10, 25810, 123610 
  4. Hexadecimal Number System : Any number having base or radix 16 and the number consists 0, 1, 2, 3, ...... 9 and character consist A, B, C, D, E and F are called hexadecimal number system. Where A=10, B=11, C=13, D=14, E=15 and F=15. E.g : 25A­16, 156B16, 9D16  

Binary Calculation

The modern digital computer system performs every calculations in the form of binary format. They present 0 or 1, on or off, presence and absent. It represents the status. 
Binary Addition: 
Binary addition is performed in a similar way to decimal addition.
Binary Addition
X
Y
X+Y
0
0
0
0
1
0
1
0
0
1
1
10 (with a carry of 1)
Example: a) Add 110102 + 1001­2    b) 111102 + 11101­2
Binary Subtraction: 
Binary subtraction, similar method is adopted as in decimal system. 
Binary Subtraction
X
Y
X-Y
0
0
0
0
1
1 (with a borrow of 1)
1
0
1
1
1
0
Example : a) 10010 - 1011          b)    1101101 - 111101
Binary Multiplication 
Binary multiplication is easier since there is no number as "carry" value. The following rule is adopted in binary multiplication. The values are added column wise as in binary addition. 
Binary Multiplication
X
Y
X*Y
0
0
0
0
1
0
1
0
0
1
1
1

Example:  a)   11101 x 111          b)    100011 x 110  


Binary Division
Binary Division is similar to decimal division. If a number cannot be divided, put 0 to the quotient. If division is possible put 1 to the quotient. Multiplication and subtraction is as discussed in binary multiplication and binary subtraction.  
 Example: a) Divide 1011 by 11               b)  111 by 11
For Practice : 

  1. Binary Addition
    • 1011 + 11 
    • 11111 + 10101
    • 11100 + 10111
  2. Binary Subtraction
    • 1011 - 1000
    • 101010 - 11001
    • 11011 - 1010 
  3. Binary Multiplication
    • 1110 x 110
    • 1101 x 111
    • 11101 x 1011
  4. Binary Division 
    • 10011 by 110
    • 11100 by 1110
    • 1110 by 110
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May 07, 2019 ,
The number of address fields in the instruction format depends on the internal organization of CPU. On the basis of no. of address field, we can categories the instruction as bellow.
  • Three Address Instruction : Memory addresses for the two operands and one destination need to be specified. It is also called General register organization. 
  • Two Address Instruction : Two address registers or two memory locations are specified. Assumes that the destination address is the same as that of the first operand. 
  • One Address Instruction : One address can be a register name or memory address. It uses AC (Accumulator) register for all data manipulation. It is also called single accumulator organization. 
  • Zero Address Instruction : Stack is used. Arithmetic operation pops two operands from the stack and pushes the result. It is also called stack organization. 


CA Assignment (MICT 1st Sem)

Write instruction of following expression using 3, 2, 1 and 0 address instruction format.

a)  Y = (A+B) * C

      Three (3) address instruction format 
         ADD R1, A, B         // R1 = M[A] + M[B]
         MUL Y, R1, C         // M[Y] = R1 * M[C]

      Two (2) address instruction format 
         MOV R1, A          // R1 = A
         ADD R1, B           // R1 = R1 + M[B]
         MOV R2, C          // R2 = M[C]
         MUL R1, R2        // R1 = R1 * R2
         MOV Y, R1          // M[Y] = R1 

      One (1) address instruction format 
        LOAD A            // AC = M[A]
        ADD B              // AC = AC + M[B]
        MUL C              // AC = AC * M[C]
        STORE Y          // M[Y] = AC 

      Zero (0) address instruction format 
        PUSH A             // TOS = M[A]
        PUSH B             // TOS = M[B]
        ADD                  // TOS = M[A] + M[B]
        PUSH C             // TOS = M[C]
        MUL                  // TOS = (M[A] + M[B]) * M[C]
        POP Y                // M[Y] = TOS

b)  Z = (A*C+D)*A

      Three (3) address instruction format 
      MUL R1, A, C          // R1 = M[A] * M[C]
      ADD R2, R1, D        // R2 = R1 + M[D]
      MUL Z, R2, A          // M[Z] = R2 * M[A] 

      Two (2) address instruction format 
       MOV R1, A          // R1 = M[A]
       MUL R1, C           // R1 = R1 * M[C]
       MOV R2, D          // R2 = M[D]
       ADD R1, R2         // R1 = R1 + R2 
       MUL R1, A           // R1 = R1 * M[A]
       MOV R1, Z           // M[Z] = R1

      One (1) address instruction format   Z = (A*C+D)*A
        LOAD A               // AC = M[A]
        MUL C                 // AC = AC * M[C]
        ADD D                 // AC = AC + M[D]
        MUL A                 // AC = AC * M[A]
        STORE Z             // M[Z] = AC
                            
      Zero (0) address instruction format 
        PUSH A              // TOS = M[A]
        PUSH C              // TOS = M[C]
        MUL                   // TOS = M[A] * M[C]
        PUSH D              // TOS = M[D] 
        ADD                   // TOS = (M[A] * M[C]) + M[D])
        PUSH A              // TOS = M[A]
        MUL                   // TOS =  (M[A] * M[C]) + M[D]) * M[A] 
        POP Z                 // M[Z] = TOS



c)  Y = {(A+B)*C}+D

      Three (3) address instruction format 
      ADD R1, A, B         // R1 = M[A] + M[B] 
      MUL R2, R1, C       // R2 = R1 * M[C]
      ADD Y, R2, D         // M[Y] = R2 + M[D]

     Two (2) address instruction format 
       MOV R1, A           // R1 = M[A]
       ADD R1, B            // R1 = R1 + M[B]
       MOV R2, C           // R2 = M[C]
       MUL R1, R2          // R1 = R1 * R2
       MOV R3, D           // R3 = M[D]
       ADD R1, R3          // R1 = R1 + R3 
       MOV Y, R1            // M[Y] = R1

      One (1) address instruction format (Y = {(A+B)*C}+D)
       LOAD A           // AC = M[A]
       ADD B              // AC = AC + M[B]
       STORE T          // M[T] = AC 
       LOAD C           // AC = M[C]
       MUL T             // AC = AC * M[T]
       ADD D             // AC = AC + M[D]
       STORE Y         // M[Y] = AC

      Zero (0) address instruction format 
        PUSH A           // TOS = M[A]
        PUSH B           // TOS = M[B] 
        ADD                // TOS = M[A] + M[B]
        PUSH C          // TOS = M[C]
        MUL                // TOS = (M[A]+M[B])*M[C]
        PUSH D          // TOS = M[D]
        ADD                // TOS = {(M[A]+M[B])*M[C]}+M[D]
        POP Y             // M[Y] = TOS
     
      
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